Last updated: September 26, 2019
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The fiction procedure of the nano-LED devices is explained in this chapter. The procedure includes doing nanogap devices and turning ZnO nanostructures between the nanogaps. Sharp tips are formed on the top Si bed of the wafer by wet chemical etching. The silicon tips are so suspended by taking the SiO2 underneath. The tips are covered with Ni after vaporization and they act as the electrical contact for the nano-LED. The nanogap between the tips is filled with Zn after another vaporization procedure. The Zn is converted to ZnO by thermic oxidization, which is the semiconducting material portion of the nano-LED for breathing visible radiation.

2.1 Fabrication of Nanogap Devices

The nanogap devices are fabricated on a SOI wafer by optical lithography and anisotropic wet chemical Si etching with a alone double-layer etch mask72.

The substrate of the SOI wafer consists of a bed of Si with the thickness of 3?m on the top, a bed of Si dioxide ( SiO2 ) with the thickness of 5?m in the center and a bottom bed of Si with the thickness of 500?m. Before fiction, a thermally adult SiO2 movie with the thickness of 0.27?m and a low emphasis LPCVD Si nitride ( SiN ) movie with the thickness of 0.5?m are deposited on the substrate. The SiN and SiO2 movies are used as masks for K hydrated oxide ( KOH ) etching. The construction of the substrate before fiction is shown in Figure 2-1-1.

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Figure 2-1-1. Wafer construction before fiction.

The overall fiction procedure includes three times of optical lithography, with the first 1 for SiN etching and the undermentioned two for Si etching.

To get down the lithography, the wafer is cleaned utilizing marauder ( H2SO4 and H2O2 ) solution and dehydrated on the hot home base at 300 & A ; deg ; C for five proceedingss. Haxamethyldisilazane ( HMDS ) bluess are applied to the wafer to heighten the adhesion of photoresist ( PR ) to the surface. The wafer is so coated with a bed of photoresist and soft baked on the hot home base at 110 & A ; deg ; C for one minute. After being exposed to UV visible radiation with the first bed of the etch mask aligned on the top for 12 seconds, the wafer is so put into the developer to fade out the open portion. The staying photoresist map as the mask for the SiN etching utilizing tetrafluoromethane ( CF4 ) plasma in a vacuity chamber for 20 proceedingss. Figure 2-1-2 shows the top position of the device after the first lithography.

Figure 2-1-2. Top position of the device after the first lithography: ( a ) before SiN etching ;

( B ) after SiN etching.

Another lithography procedure is conducted for the first measure of Si etching. After being coated with photoresist and soft baked at 110 & A ; deg ; C for one minute, the wafer is aligned under the 2nd bed of the etch mask and exposed to UV visible radiation for 8 seconds. The 2nd clip of baking is conducted at 130 & A ; deg ; C for two proceedingss before the wafer is exposed to UV visible radiation without the etch mask for 30 seconds. After developing, the staying photoresist has the form of the reverse image of the etch mask. The open part of the SiO2 is removed with buffered oxide etch ( BOE ) solution and the bare underlying Si is etched by KOH solution. The KOH solution has the concentration of 30 % and the etch rate is 0.31?m per minute at 60 & A ; deg ; C. Figure 2-1-3 shows the construction of the device after the 2nd lithography. The KOH solution keeps etching the Si bed until the breadth of the Si cantilever beam on the top Si bed is approximately 2.5 to 3?m. A thermic oxidization procedure is conducted and a bed of SiO2 is formed on the surface of the open portion of the Si bed in order to forestall the Si from being farther etched in the 2nd KOH etching.

Figure 2-1-3. Top position of the device after the 2nd lithography: ( a ) before SiO2 etching ; ( B ) after SiO2 etching ; ( degree Celsius ) after taking photoresist ;

( vitamin D ) after Si etching by utilizing KOH solution.

The following measure of fiction is the 3rd lithography. The procedures of wafer cleansing, photoresist coating and soft baking are similar as those in the first lithography. The 2nd bed of the etch mask is used during the exposure to the UV visible radiation for 20 seconds. After development, the staying photoresist has the exact transcript of the form on the etch mask. The exposed SiO2 is etched utilizing BOE solution and the Si underneath is etched by KOH solution for about 1 hr. After etching, the surface bed of the bare Si is converted to SiO2 by another oxidization procedure. The intent of the oxidization is to protect the Si from being etched during the undermentioned SiN etching. Then the SiN bed is removed by phosphoric. The SiO2 bed under the SiN and the exposed part of the SiO2 on top of the bottom Si are both removed by BOE solution. Figure 2-1-4 shows the construction of the device after the 3rd lithography.

Figure 2-1-4. Top position of the device after the 3rd lithography: ( a ) before SiO2 etching ; ( B ) after SiO2 etching ; ( degree Celsius ) after taking photoresist and Si etching

by KOH solution ; ( vitamin D ) after taking SiN and SiO2.

The nanogap device is shown in Figure 2-1-5. As can be seen in the figure, crisp tips are fabricated on the top Si bed of the device. The tips are formed by the ( 111 ) Si crystal plane created during the first KOH etching and ( 100 ) plane created during the 2nd KOH etching. There are nanoscale spreads between the crisp tips and the mean size of the spreads is a few 10s of nanometres.

Figure 2-1-5. Top position of the S1 nanogap device and shut up position of the nanogap.

Four different designs of nanogap devices are fabricated together on one wafer. The constellation shown in Figure 2-1-5 is named as S1 device. Figure 2-1-6 shows the constellation of the S2 nanogap device.

Figure 2-1-6. Top position of the S2 nanogap device and the close up position of the nanogap.

The size of the nanogap can be estimated utilizing Simmon ‘s Model. A MATLAB plan has been made to cipher the spread size. Details about the Simmon ‘s Model and the plan are in the appendix.

2.2 Growth of ZnO Nanostructures between Nanogaps

ZnO nanostructures are synthesized between the nanogaps by the thermic vaporization of Ni and Zn and the thermic oxidization of Zn.

After doing nanogap devices, a bed of Ni with the thickness of 30nm and a bed of Zn with the thickness of 50nm are thermally evaporated on the devices in a vacuity of ~10-7 Torr. After that, the Zn movie on the devices is oxidized to ZnO movie in a vitreous silica tubing furnace with an O flow of 5 sccm at 350a„? ( Figure 2-2-1 ) . Figure 2-2-2 shows the cross-sectional position of the device before and after the metal vaporization and the Zn oxidization.

Figure 2-2-1. Lindberg/Blue M vitreous silica tubing furnace.

Figure 2-2-2. Cross-sectional position of the device: ( a ) nanogap device ; ( B ) device after vaporization of Ni and Zn ; ( degree Celsius ) device after oxidization.

Different sorts of metals have been considered as the electrode stuff for the nano-LED devices. However, metal may be formed between Zn and other metals like aluminium and Cu during the thermic oxidization procedure because of the high temperature. Compared with them, Ni react less with Zn at elevated temperature. As a consequence, Ni is preferred to execute the electrical contact for our device.

The images of the nanogap taken by scanning negatron microscope ( SEM ) are shown in Figure 2-2-3.

Figure 2-2-3. SEM images of the nanogap: ( a ) close-up position of the spread ;

( B ) after vaporization and oxidization.

As can be seen in the image, the nanogap is filled with ZnO after the vaporization of Ni and Zn and the Zn oxidization.